1. Field of Invention
The present invention relates to a sense amplifier. More particularly, the present invention relates to a sense amplifier circuit capable of accelerating the latching speed of the sense amplifier, thereby increasing the operating speed of a semiconductor memory device.
2. Description of Related Art
Data within a particular memory unit of a semiconductor memory such as dynamic random access memory (DRAM) are generally amplified and read out by a sense amplifier. The sense amplifier is connected to a bit line of a memory cell array so that any particular cell can be addressed.
FIG. 1 is a circuit diagram of a conventional sense amplifier. The sense amplifier 10 consists of a pair of NMOS transistors 12, 14 and a pair of PMOS transistors 16, 18. Interconnections of the transistors are shown in FIG. 1. The sense amplifier 10 is connected to bit lines BL and BLB of a memory cell array (not shown in the figure) for reading and amplifying the data from a selected memory cell. The bit line BLB is a complementary bit line. The sense amplifier 10 is also connected to data lines DL and DLB via NMOS transistors 20 and 22, respectively. The data line DLB is also a complementary data line. On/off states of the NMOS transistors 20 and 22 are determined by the voltage of a column address line COL. In FIG. 1, labels NSA and PSA are points for inputting complementary sense amplifier enable signals.
In the prior art, when the sense amplifier 10 is writing data into the memory, the complementary data line DLB must be kept at a low voltage level in order to latch the amplifier 10. As the operating voltage drops during the writing cycle, the complementary data line DLB reaches the low potential level demanded by the sense amplifier 10 only slowly due to the presence of a pass gate. A consequence is that data may only be partially written into the memory.